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19-5480; Rev 8/10
DS1553
64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
www.maxim-ic.com
GENERAL DESCRIPTION
The DS1553 is a full-function, year-2000compliant (Y2KC) real-time clock/calendar (RTC) with an RTC alarm, watchdog timer, power-on reset, battery monitor, and 8k x 8 nonvolatile static RAM. User access to all registers within the DS1553 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically.
FEATURES
Integrated NV SRAM, RTC, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the 16 Top RAM Locations Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power Precision Power-On Reset Programmable Watchdog Timer and RTC Alarm BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the Year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for 10% VCC Power-Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time PIN-PACKAGE 28 EDIP (0.740) 28 EDIP (0.740) 28 EDIP (0.740) 28 EDIP (0.740) 34 PowerCap* 34 PowerCap* 34 PowerCap* 34 PowerCap* -- TOP MARK** DS1553+85 DS1553+100 DS1553W+120 DS1553W+150 DS1553P+85 DS1553P+100 DS1553WP+120 DS1553WP+150 DS9034PCX

Pin Configurations appear at end of data sheet.
ORDERING INFORMATION
PART DS1553-85+ DS1553-100+ DS1553W-120+ DS1553W-150+ DS1553P-85+ DS1553P-100+ DS1553WP-120+ DS1553WP-150+ DS9034PCX+ VOLTAGE (V) 5.0 5.0 3.3 3.3 5.0 5.0 3.3 3.3 3 TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C
+Denotes a lead(Pb)-free/RoHS-compliant package. *PowerCap required, must be ordered separately
**A "+" symbol anywhere on the top mark indicates a lead(Pb)-free package.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PIN DESCRIPTION
EDIP 1 2 3 4 5 6 7 8 9 10 21 23 24 25 11 12 13 15 16 17 18 19 20 22 26 27 28 -- PIN PowerCap 2 30 25 24 23 22 21 20 19 18 28 29 27 26 16 15 14 13 12 11 10 9 8 7 1 6 5 17 2, 3, 31-34 NAME RST A12 A7 A6 A5 A4 A3 A2 A1 A0 A10 A11 A9 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE OE IRQ/FT WE VCC GND N.C FUNCTION Active-Low Power-On Reset Output (Open Drain)
Address Inputs
Data Input/Outputs
Active-Low Chip Enable Active-Low Output Enable Active-Low Interrupt/Frequency Test Output (Open Drain) Active-Low Write Enable Power-Supply Input Ground No Connection
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
DETAILED DESCRIPTION
The RTC registers in the DS1553 are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated. This occurs regardless of external registers settings to guarantee that accurate RTC information is always maintained. The DS1553 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity. The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wakeup. Either the IRQ /FT or RST outputs can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt or reset output is activated if the correct activity is not detected within programmed limits. The DS1553 power-on reset can be used to detect a system power-down or failure and can hold the CPU in a safe reset state until normal power returns and stabilizes. The RST output is used for this function. The DS1553 also contains its own power-fail circuitry, which automatically deselects the device when the VCC supply enters an out-of-tolerance condition. This feature provides a high degree of data security during unpredictable system operation brought on by low VCC levels.
PACKAGES
The DS1553 is available in a 28-pin DIP and a 34-pin PowerCap module. The 28-pin DIP module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1553P after completion of the surface-mount process. Mounting the PowerCap after the surface-mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. Figure 1. Block Diagram
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Table 1. Operating Modes
VCC CE VIH VCC > VPF VIL VIL VIL VSO < VCC DATA READ MODE
The DS1553 is in read mode whenever CE (chip enable) is low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data is available at the data input/output (DQ) pins within tAA after the last address input is stable, provided that CE and OE access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access time (tOEA). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for output data hold time (tOH) but will then go indeterminate until the next address access.
DATA WRITE MODE
The DS1553 is in write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible, and data can be written and read only when VCC is greater than VPF. However, when VCC is below the power-fail point (VPF)--the point at which write protection occurs--the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
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below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1553 has a lithium power source that is designed to provide energy for the clock activity and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running in the absence of VCC. Each DS1553 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation.
INTERNAL BATTERY MONITOR
The DS1553 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF) bit of the Flags register (B4 of 1FF0h) is not writeable and should always be 0 when read. If a 1 is ever present, an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the VCC level. When VCC falls to the power-fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST signal continues to be pulled low for 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and is therefore operational whether or not the oscillator is enabled.
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CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions. Table 2. Register Map
ADDRESS
B7 X X X X X OSC W WDS AE AM4 AM3 AM2 AM1 Y WF
1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 1FF7h 1FF6h 1FF5h 1FF4h 1FF3h 1FF2h 1FF1h 1FF0h
B6 B5 10 Year X X 10 M X 10 Date FT X X X 10 Hour 10 Minutes 10 Seconds R 10 Century BMB BMB3 BMB2 4 Y ABE Y Y 10 Date Y 10 Hours 10 Minutes 10 Seconds Y Y Y AF 0 BLF
DATA B4 B3
X
BMB 1 Y
Y 0
B2 B1 Year Month Date Day Hour Minutes Seconds Century BMB RB 0 1 Y Y Date Hours Minutes Seconds Y Y 0 0
B0
FUNCTION/RANGE Year Month Date Day Hour Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-39
RB0 Y
Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Unused Flags 01-31 00-23 00-59 00-59 -- --
Y 0
X = Unused, Read/Writable Under Write and Read Bit Control FT = Frequency Test Bit OSC = Oscillator Start/Stop Bit W = Write Bit R = Read Bit WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits
AE = Alarm Flag Enable Y = Unused, Read/Writable Without Write and Read Bit Control ABE = Alarm in Battery-Backup Mode Enable AM1-AM4 = Alarm Mask Bits WF = Watchdog Flag AF = Alarm Flag 0 = 0 Read Only BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB of the Seconds register (B7 of 1FF9h). Setting it to 1 stops the oscillator; setting it to 0 starts the oscillator. The DS1553 is shipped from Dallas Semiconductor with the clock oscillator turned off, with the OSC bit set to 1.
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READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state, allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h). As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers resume within 1 second after the read bit is set to 0 for a minimum of 500s. The read bit must be 0 for a minimum of 500s to ensure the external registers are updated.
SETTING THE CLOCK
The 8th bit, B7 of the Control register, is the write bit. Setting the write bit to 1, like the read bit, halts updates to the DS1553 (1FF8h-1FFFh) registers. After setting the write bit to 1, RTC registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to 0 then transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1553 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. The electrical environment also affects clock accuracy and caution should be taken to place the RTC in the lowest level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks, available on our website at www.maxim-ic.com/appnoteindex.com.
CLOCK ACCURACY (PowerCap MODULE)
The DS1553 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module typically keeps time accuracy to within 1.53 minutes per month (35ppm) at +25C. The electrical environment affects clock accuracy and caution should be taken to place the RTC in the lowest level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks, available on our website at www.maxim-ic.com/appnoteindex.com.
FREQUENCY TEST MODE
The DS1553 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the IRQ /FT output toggles at 512Hz when the FT bit is 1, the Alarm Flag Enable bit (AE) is 0, and the Watchdog Steering bit (WDS) is 1 or the Watchdog register is reset (Register 1FF7h = 00h). The IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to 0 on power-up.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
USING THE CLOCK ALARM
The alarm settings and control for the DS1553 reside within registers 1FF2h-1FF5h. Register 1FF6h contains two alarm-enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm condition. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1553 is in the battery-backed state of operation to serve as a system wakeup. Alarm mask bits AM1-AM4 control the alarm mode. Table 3 shows the possible settings. Configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting. Table 3. Alarm Mask Bits
AM4 1 1 1 1 0 AM3 1 1 1 0 0 AM2 1 1 0 0 0 AM1 1 0 0 0 0 ALARM RATE Once per second When seconds match When minutes and seconds match When hours, minutes, and seconds match When date, hours, minutes, and seconds match
When the RTC register values match Alarm register settings, the Alarm Flag bit (AF) is set to 1. If the Alarm Flag Enable (AE) is also set to 1, the alarm condition activates the IRQ /FT pin. The IRQ /FT signal is cleared by a read or write to the Flags register (Address 1FF0h) as shown in Figures 2 and 3. When CE is active, the IRQ /FT signal may be cleared by having the address stable for as short as 15ns and either OE or WE active, but it is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is also cleared by a read or write to the Flags register, but the flag does not change states until the end of the read/write cycle and the IRQ /FT signal has been cleared.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Figure 2. Clearing IRQ Waveforms
CE ,
Figure 3. Clearing IRQ Waveforms
CE = O
The IRQ /FT pin can also be activated in the battery-backed mode. The IRQ /FT goes low if an alarm occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition, however, an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing during the battery-backup mode and power-up states. Figure 4. Backup Mode Alarm Waveforms
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USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog timer by setting the desired amount of timeout into the 8-bit Watchdog register (Address 1FF7h). The five Watchdog register bits BMB4-BMB0 store a binary multiplier and the two lower-order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the Watchdog register = 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF) is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or the Watchdog register (1FF7) is read or written. The most significant bit of the Watchdog register is the Watchdog Steering Bit (WDS). When set to 0, the watchdog activates the IRQ /FT output when the watchdog times out. When WDS is set to 1, the watchdog outputs a negative pulse on the RST output for 40ms to 200ms. The Watchdog register (1FF7) and the FT bit are reset to 0 at the end of a watchdog timeout when the WDS bit is set to 1. The watchdog timer resets when the processor performs a read or write of the Watchdog register. The timeout period then starts over. Writing a value of 00h to the Watchdog register disables the watchdog timer. The watchdog function is automatically disabled upon power-up and the Watchdog register is cleared. If the watchdog function is set to output to the IRQ /FT output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to 0: WDS = 0, BMB0-BMB4 = 0, RB0-RB1 = 0, AE = 0, and ABE = 0.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.....................................................-0.3V to +6.0V Storage Temperature Range EDIP .................................................................................................-40C to +85C PowerCap.........................................................................................-55C to +125C Lead Temperature (soldering, 10s)..........................................................................................+260C (Note: EDIP is hand or wave-soldered only.) (Note 8) Soldering Temperature (reflow)............................................................................................+260C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RANGE Commercial TEMP RANGE 0C to +70C VCC 3.3V 10% or 5V 10%
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the operating range.)
PARAMETER Logic 1 Voltage All Inputs Logic 0 Voltage All Inputs VCC = 5V 10% VCC = 3.3V 10% VCC = 5V 10% VCC = 3.3V 10% SYMBOL VIH VIH VIL VIL MIN 2.2 2.0 -0.3 -0.3 TYP MAX VCC + 0.3V VCC + 0.3V +0.8 +0.6 UNITS V V NOTES 1 1 1 1
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER Active Supply Current TTL Standby Current (CE = VIH) CMOS Standby Current (CE VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) IOUT = 2.1mA, DQ0-7 Outputs Output Logic 0 Voltage IOUT = 7.0mA, IRQ/FT and RST Outputs Write Protection Voltage Battery Switchover Voltage SYMBOL ICC ICC1 ICC2 IIL IOL VOH VOL1 VOL2 VPF VSO 4.20 VBAT -1 -1 2.4 0.4 0.4 4.50 MIN TYP 15 1 1 MAX 50 3 3 +1 +1 UNITS mA mA mA A A V V V V V 1 1 1, 5 1 1, 4 NOTES 2, 3 2, 3 2, 3
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER Active Supply Current TTL Standby Current (CE = VIH) CMOS Standby Current (CE VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) IOUT = 2.1mA, Output Logic 0 DQ0-7 Outputs Voltage IOUT = 7.0mA, IRQ/FT and RST Outputs Write Protection Voltage Battery Switchover Voltage SYMBOL ICC ICC1 ICC2 IIL IOL VOH VOL1 VOL2 VPF VSO 2.75 VBAT or VPF -1 -1 2.4 0.4 0.4 2.97 MIN TYP 10 0.7 0.7 MAX 30 2 2 +1 +1 UNITS mA mA mA A A V V V V V 1 1 1, 5 1 1, 4 NOTES 2, 3 2, 3 2, 3
Figure 5. Read Cycle Timing Diagram
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READ CYCLE, AC CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the operating range.) 85ns ACCESS PARAMETER SYMBOL MIN MAX Read Cycle Time Address Access Time CE to DQ Low-Z CE Access Time CE Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH 5 5 45 30 5 5 85 30 5 55 35 85 85 5 100 35 100ns ACCESS MIN 100 100 MAX UNITS ns ns ns ns ns ns ns ns ns
READ CYCLE, AC CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER Read Cycle Time Address Access Time CE to DQ Low-Z CE Access Time CE Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address
SYMBOL tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH
120ns ACCESS MIN MAX 120 120 5 120 40 5 100 35 5
150ns ACCESS MIN MAX 150 150 5 150 50 5 130 35 5
UNITS ns ns ns ns ns ns ns ns ns
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
WRITE CYCLE, AC CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER Write Cycle Time Address Access Time WE Pulse Width CE Pulse Width Data Setup Time Data Hold time Address Hold Time WE Data Off Time Write Recovery Time SYMBOL tWC tAS tWEW tCEW tDS tDH tAH tWEZ tWR 85ns ACCESS MIN 85 0 65 70 35 0 5 30 5 5 MAX 100ns ACCESS MIN 100 0 70 75 40 0 5 35 MAX UNITS ns ns ns ns ns ns ns ns ns
WRITE CYCLE, AC CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER Write Cycle Time Address Setup Time WE Pulse Width CE Pulse Width Data Setup Time Data Hold Time Address Hold Time WE Data Off Time Write Recovery Time SYMBOL tWC tAS tWEW tCEW tDS tDH tAH tWEZ tWR 10 120ns ACCESS MIN 120 0 100 110 80 0 0 40 10 MAX 150ns ACCESS MIN 150 0 130 140 90 0 0 50 MAX UNITS ns ns ns ns ns ns ns ns ns
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Figure 6. Write Cycle Timing, Write-Enable Controlled
Figure 7. Write Cycle Timing, Chip-Enable Controlled
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER CE or WE at VIH, Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Fall Time: VPF(MIN) to VSO VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data Retention Time (Oscillator On) SYMBOL tPD tF tFB tR tREC tDR MIN 0 300 10 0 40 10 200 TYP MAX UNITS s s s s ms years 6, 7 NOTES
Figure 8. Power-Up/Down Waveform Timing 5V Device
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER CE or WE at VIH, Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data Retention Time (Oscillator On) SYMBOL tPD tF tR tREC tDR MIN 0 300 0 40 10 200 TYP MAX UNITS s s s ms years 6, 7 NOTES
Figure 9. Power-Up/Down Waveform Timing 3.3V Device
CAPACITANCE
(TA = +25C)
PARAMETER Capacitance on All Input Pins Capacitance on IRQ/FT, RST, and DQ Pins SYMBOL CIN CIO MIN TYP MAX 7 10 UNITS pF pF NOTES 1 1
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AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
NOTES:
Voltage referenced to ground. Typical values are at +25C and nominal supplies. Outputs are open. Battery switch over occurs at the lower of either the battery voltage or VPF. The IRQ /FT and RST outputs are open drain. Data retention time is at +25C. Each DS1553 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 8) Real-time clock modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap: a. Maxim recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up ("live-bug"). b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. 1) 2) 3) 4) 5) 6) 7)
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PIN CONFIGURATIONS
TOP VIEW RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 28 1 27 2 3 DS1553 26 25 4 24 5 23 6 22 7 21 8 20 9 19 10 18 11 17 12 16 13 14 15 VCC WE IRQ/FT A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 IRQ/FT N.C. N.C. RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 N.C. N.C. N.C. N.C. A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DS1553
X1
GND VBAT
X2
28-Pin Encapsulated Package (700-mil Extended)
34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap)
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. 21-0241 21-0246 LAND PATTERN NO.
28 EDIP 34 PWRCP
MDP28+2 PC1+2
-- --
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REVISION HISTORY
REVISION DATE DESCRIPTION Updated the Ordering Information table; updated the storage and soldering temperatures and added the lead temperature in the Absolute Maximum Ratings section; changed 70ns Access to 85ns Access in the Read Cycle, AC Characteristics (5V) table and updated the min/max values for tRC, tAA, tCEA, tCEZ, tOEA, and tOEZ; changed 70ns Access to 85ns Access in the Write Cycle, AC Characteristics (5V) table and updated the min/max values for tWC, tWEW, tCEW, tDS, and tWEZ; updated the Package Information table and removed the package drawings PAGES CHANGED
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Price & Availability of DS1553P-100

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